This application claims the priority of Japanese Patent Application No. Hei 9-81470, filed Mar. 31, 1997, which is incorporated herein by reference in its entirety.
The invention relates generally to video signal processing.
In the television industry, the Picture In Picture (xe2x80x9cPIPxe2x80x9d) function is a well-known function used to display multiple pictures on a screen or window. Future multimedia applications, however, demand additional display functions. For example, performing a window display function at an arbitrary reduction ratio, as widely developed in the operating environment of the personal computer, is demanded in the television industry as well. To display other pictures on the window, a buffer memory such as a field memory or a frame memory for synchronizing the picture and the picture is required.
As shown in the reduced video signal processing circuit of FIG. 1, an input video signal of a picture is entered into an input processor. The picture is reduced according to reduction ratio data K by using an internal filter circuit 10 so that the reduced video signal is transmitted to field memories 2, 3. A control block 4 includes an input video clock generator 5 for controlling performance of a write function to the field memories 2, 3, and a display video clock generator 6 for controlling performance of a read function from the field memories 2, 3. The reduction ratio data K is fed from an external source to the input video clock generator 5, from which they are entered into the input processor 1.
The input video clock generator 5 receives a horizontal synchronizing signal (xe2x80x9cH inputxe2x80x9d) and a vertical synchronizing signal (xe2x80x9cV inputxe2x80x9d) of the input video signal and generates a write clock signal, WCLK, having the same rate as that of a pixel clock synchronized with the H input. The input video clock generator 5 also generates write enable signals, WE1 and WE2, for enabling the field memories 2, 3 alternately at the field unit for an effective display period of the input video signal. Additionally, the input video clock generator 5 generates a write reset signal, WRST, for resetting the write addresses of the field memories 2, 3 at the rise of the write enable signals. The field memories 2, 3 are equipped individually with address counters for designating the write and read addresses independently. The writing address counter is reset by the signal WRST and increments the write addresses by counting the write clock signals WCLK while the enable signals WE1 and WE2 are at a high level. The reduced video signal from the input processor 1 then is written in the field memories 2, 3.
When the value of the reduction ratio data K is at 1, in other words, when there is no reduction, the write enable signals WE1 and WE2 are kept at the high level for the effective video period. When the reduction ratio data K is lower than 1, the reduction ratio data K is used to control when the enable signals WE1 and WE2 are high. If, for example, the value of the reduction ratio data K is xc2xd, the high level and the low level are repeated at alternating pixels, as shown at FIG. 2(b) and FIG. 2(c).
The input video clock generator 5 calculates image size data SIZ on the basis of the reduction ratio data K and transmits the data SIZ to the display video clock generator 6. If the number of horizontal pixels and the number of vertical pixels from the input video signal are 640 and 480, respectively, and if the reduction ratio data K is xc2xd, the image size data SIZ are 320 and 240 for the horizontal SIZ(H) and the vertical SIZ(V), respectively.
To read the reduced video signals from the field memories 2, 3, the display video clock generator 6 receives both the horizontal synchronizing signal (xe2x80x9cH displayxe2x80x9d) and the vertical synchronizing signal (xe2x80x9cV displayxe2x80x9d) from the display video signals. Alternatively, the display video clock generator 6 can receive the picture and the display position data (X, Y) indicating the window display position of the reduced image. The display video clock generator 6 generates a read clock signal RCLK at the same rate as that of the pixel clock synchronized with the H display. The display video clock generator 6 also generates read enable signals RE1 and RE2 enabling the field memories 2, 3 alternately at the unit of field for the effective display period of the display video signals. Additionally, the display video clock generator 6 generates a read reset signal RRST for resetting the read addresses of the field memories 2, 3 at the rise of the read enable signals. The reading address counters in the field memories 2, 3 are reset by the signal RRST and increment the read addresses by counting the read clocks RCLK while the enable signals RE1 and RE2 are at the high level. The reduced video signals then are read from the field memories 2, 3.
The H display and the V display may be generated, if known in advance, by the display video clock generator 6 so that the various signals RRST, RCLK, RE1 and RE2 can be generated on the basis thereof.
As indicated by FIG. 4, the display position data (X, Y) indicates the display position of the picture (of the display video signal), and the image size data SIZ(H), SIZ(V) indicates the size of the picture (of the input video signals) to be displayed on the window. Based on the image size data SIZ(H), SIZ(V) and the image position data (X, Y), the display video clock generator 6 sets the read enable signals RE1, RE2 to the high level only for the effective display period so that the display of FIG. 4 can be realized (see FIG. 2(e) and FIG. 2(f)). In contrast to the input side, the high level signals are generated continuously.
The image size data SIZ(V), SIZ(H) and the image position data (X, Y) are transmitted from the display video clock generator 6 to a display processor 7 located downstream of the field memories 2, 3. The display processing for the window display, such as the framing of the reduced video signals or the addition of background data, is performed by the display processor 7, and the result is provided as display video signals.
To change the reduction ratio arbitrarily, the processing content has to be changed at both the write side and the read side according to the reduction ratio data. However, the displayed image is disturbed if the processing content is changed during performance of the writing and reading functions. To prevent this disturbance, the change in the reduction ratio is performed during a vertical blanking interval.
There is a delay with respect to the change in the reduction ratio between the write side and the read side because the V input and the V display are not synchronized. If new reduction ratio data K is entered at a time T1 when the phase of the V display is delayed from the V input (see FIG. 2(f)), the reduction ratio data K is changed at the input video clock generator 5 and the input processor 1 during a vertical blanking interval NP1, after T1 (see FIG. 2(a)). The subsequent display reduction and the write control are performed according to the changed reduction ratio. In the display video clock generator 6 and the display processor 7, however, the reduction ratio is changed during a vertical blanking interval DP1, after T1 (see FIG. 2(d)). The interval DP1 occurs after the interval NP1 so that the video signals, as written according to the changed reduction ratio, are subjected to the display processing during and after the interval DP1.
If, however, the new reduction ratio data K is entered at a time T2 after the vertical blanking interval NP1 at the V input but before the vertical blanking interval DP1 at the V display (see FIG. 3), the reduction ratio is changed in the input video clock generator 5 and the input processor 1 during a vertical blanking interval NP2, after T2 (see FIG. 3(a)). In the display video clock generator 6 and the display processor 7, however, the change in the reduction ratio data K is performed during the vertical blanking interval DP1, before NP2, in other words, prior to the change in the reduction ratio data K at the input side. For the display period following the interval DP1, the video signals prior to the change in the reduction ratio data K should be displayed without a change in the magnification. Instead, however, the video signals will be reduced according to the image size data, thereby causing distortions in the image displayed on the window or screen. The reduction ratio data K, therefore, cannot be changed if the window is displayed continuously.
In Japanese Patent Application No. 7-267107, we have proposed a reduced video signal processing circuit for controlling the reading of a reduced video signal, if the reduction ratio data is changed by writing the image size data as a header together with the reduced video signals in a buffer memory and by reading the image size data at the display side.
According to this construction, after the image size data are fixed, the display can be processed reliably at the display side at a new reduction ratio from the video signals for which the reduction ratio has been changed. The image size data are determined by counting the horizontal write enable signal WEH and the vertical write enable signal WEV for generating the write enable signals WE1 and WE2, respectively, for one horizontal period of the H input and for a one-field period of the V input. For the one-field period just following the change in the reduction ratio, the video signal itself is processed at the new reduction ratio, but the image size data cannot add the data after the change in the reduction ratio thereto. Thus, the reduction ratios between the reduced video signal to be written in the buffer memory and the image size data are different. Such problems can occur when an image is magnified, as well as when the image is reduced.
In general, according to one aspect of the invention, a video signal processing circuit includes an input processor configured to modify an input video signal in accordance with image magnification data and a buffer memory for storing the modified video signal. The processing circuit further includes a write control unit coupled to an output of the input processor and configured to control a write function to the buffer memory by generating a write control signal in accordance with the image magnification data. The write control unit includes a calculating circuit configured to calculate image size data on the basis of a write control signal in response to a change in the image magnification data. The write control circuit also includes an inhibit circuit configured to inhibit the write function to the buffer memory while the calculation circuit calculates the image size data. In addition, the processing circuit includes a display processor coupled to the buffer memory and configured to read the modified video signal from the buffer memory. The processing circuit further includes a read control unit for controlling reading from the buffer memory in accordance with the calculated image size data.
According to another aspect of the invention, a method of processing an input video signal includes receiving image magnification data and modifying the input video signal in accordance with the image magnification data. The method further includes calculating image size data based on the image magnification data and inhibiting writing the modified video signal to a buffer memory at least during calculation of the image size data.
In various implementations, one or more of the following features are present. The calculated image size data can be transmitted to the buffer memory together with the modified video signal. For example, the image size data can be transmitted as part of a header.
The processing circuit can be configured to receive a change in image magnification data only during predetermined intervals when information cannot be written to the buffer memory. Writing the video signal to the buffer memory can be inhibited during a period commencing with one such predetermined interval which immediately follows the change in the image magnification data and ending when a next predetermined interval begins.
In some implementations, the image magnification data can represent a number equal to or less than one, and the input processor can be configured to reduce or enlarge the input video signal in accordance with the image magnification data.
A display processor can be configured to read the calculated image size data from the buffer memory and to transmit the calculated image size data to the read control unit. The read control unit can be configured to receive display position data and to transmit the display position data to the display processor. The display processor can transmit the modified video signal for display on a television screen in accordance with the display position data.
One or more of the following advantages can be provided by various implementations of the invention. Generally, by inhibiting the write function in the field memories for the period just after the change in the image magnification data, the image size data and the modified video signals can be provided to the display side of the system more accurately. The change in the image magnification can be handled reliably regardless of the timing of the change. Thus, the image magnification can be changed while the reduced or enlarged image remains displayed on the window. The invention can be used in connection with reducing or enlarging an image.